This invention relates to receivers for optical communications systems. More particularly, this invention relates to a matched-filter receiver for an optical communications system that is capable of handling fixed and/or variable data rates.
High-speed receivers for free-space and fiberoptic-based optical communications systems generally include a detector that is connected to a transimpedance amplifier that has an output connected to a low pass filter. A binary decision circuit is connected to the low pass filter. Sometimes the low pass filter is integrated with the transimpedance amplifier circuit. This arrangement approximates the performance of matched-filter designs that are known to be an optimal method for detecting signals. However, this arrangement emphasizes high-frequency noise more than the optimal matched-filter design and therefore results in lower receiver sensitivity.
Conventional matched-filter receiver designs also trade off signal-to-noise (S/N) and receiver sensitivity in order to achieve wider bandwidths that are required by high-speed data communications. In the transimpedance amplifier, a resistor and its stray capacitances define a time constant for the receiver. Oftentimes the design employs a low-value resistor to provide a relatively small time constant that is required for high-speed data communications. The use of the low-valued resistor, however, increases the current noise generated by the resistor. The current noise typically dominates the noise performance of the receiver.
Receiver designs may also need to accommodate multiple data rates. The conventional receiver designs that employ the transimpedance amplifier, the low pass filter and the current-to-voltage conversion resistor optimize performance for a single data rate only. A significant decrease in receiver sensitivity results if the receiver is used for multiple data rates.
A matched filter receiver according to the invention includes a detector that generates a current signal based on light input thereto. An integrating circuit has an input that is connected to the detector. The integrating circuit integrates the current signal and outputs an integrated signal. A delay circuit is connected to an output of the integrating circuit. The delay circuit delays the integrated signal for a first duration. A comparator circuit includes an inverting input that is connected to the output of the integrating circuit and to an output of the delay circuit.
According to other features of the invention, the comparator provides an output signal having one of a first state and a second state. The matched-filter receiver further includes a decision circuit that is connected to the comparator and that provides a binary decision signal. A clock circuit provides a clock signal having clock edges. The decision circuit includes a flip-flop circuit that is connected to the clock circuit. The flip-flop circuit latches the output of the comparator immediately following at least one of the clock edges.
According to still other features of the invention, the integrating circuit includes a resistor having a parasitic capacitance. The resistor has a resistance value that is greater than or equal to 50 kilo ohms. The integrating circuit includes an amplifier circuit that amplifies the integrated signal.
According to other features of the invention, the duration that the delay circuit delays the integrated signal can be set to a plurality of duration values.